1. Field of the Invention
This invention relates to an electronic circuit and more particularly to a synchronized clocking disable and enable circuit.
2. Background of the Relevant Art
A clocking circuit used for generating a plurality of pulses is well known. The pulses are preferably produced with extreme regularity and are often synchronized with the operation of digital circuits attached to the output of the clocking circuit. The clocking pulses are thereby used to control the speed of operation of the digital circuits which may be contained on the same monolithic circuit as that of the clocking circuit.
In order to ensure optimal performance of the digital circuit receiving the pulses, each pulse must have a set duration and the duration must not substantially vary. For example, a high level voltage pulse must remain high for a minimum duration but not to exceed that of a maximum duration. Likewise, a low level voltage pulse must also remain low more than and less than a minimum and maximum duration, respectively. If a high or low pulse is less than an acceptable time duration, then a "glitch" may occur causing possible failure of the connected digital circuits.
It is oftentimes desirable to temporarily disable the stream of clocking pulses produced from the clocking circuit. By disabling the clocking pulses, certain attached digital circuits can be temporarily placed in a halt condition. For example, microprocessor or microcontroller operations can generally be halted in such a manner. To perform a temporary disable of the clocking pulses, a clocking disable and enable circuit is generally placed between the clocking circuit and the corresponding digital circuits. The clocking disable and enable circuit receives free-running, continuous periods of clocking pulses, and also receives a disable signal which can exceed several clocking periods. When the disable signal is activated, the clocking disable and enable circuit sends to the digital circuits a steady state output indicating a momentary halt of clocking pulses. During the time in which the clocking disable and enable circuit receives the disable signal, a transitional glitch often occurs in the output of conventional disable and enable circuits causing the connected digital circuits to malfunction. The glitch, defined herein as a clocking pulse having a duration less than the target pulse duration, may cause the attached digital circuits to lose or misplace operational status or data (stored or modulated data). Accordingly, many conventional disable and enable circuits generally provide one or more glitches each time the output transitions from the clocking state to the disable or steady state. Likewise, when the disable and enable circuit re-enables clock pulses, one or more glitches may also appear at the output during transitions from the steady state to the clocking state.